The present invention relates to a CMOS static storage cell. It can be used in the microelectronics field for producing random access memories, particularly for storing binary information.
CMOS (complementary metal-oxide-semiconductors) static memories or stores, constituted solely by MOS transistors with a N channel and MOS transistors with a P channel have the advantage of consuming very little electric power and of having a high immunity to interference, particularly that of an electrical nature. However, they have a relatively low integration density.
This low integration density is particularly due to the presence in each storage cell of several electric contact holes necessary for the interconnections of the various transistors forming a storage cell. These contact holes are formed in an insulating layer, particularly of silicon oxide, deposited on the complete circuit. A further problem is caused by the guards necessary for the positioning of these contact holes. This is illustrated by the attached FIGS. 1 and 2, which respectively show the electrical diagram of a CMOS storage cell according to the prior art, and in plan view the organization of the various layers constituting this cell.
The storage cell comprises a bistable element or flip-flop 2 formed from two MOS transistors T.sub.1 and T.sub.2 with a P channel and two MOS transistors T.sub.3 and T.sub.4 with a N channel, which are electrically interconnected.
This storage cell also comprises two MOS transistors T.sub.5 and T.sub.6 with a N channel constituting the transistors for operating the bistable element 2 of the cell.
As shown in FIGS. 1 and 2, the sources S.sub.1 and S.sub.2 of transistors T.sub.1 and T.sub.2 are interconnected by means of an interconnection line 4, diffused in the substrate on which the cell is formed, and are raised to a positive potential V supplied by a not shown, electric power source. Moreover, the gates of transistors T.sub.1 and T.sub.3, designated G.sub.1 and G.sub.3 (FIG. 1) are electrically interconnected, and so are gates G.sub.2 and G.sub.4 of transistors T.sub.2 and T.sub.4.
The connection of the gates of transistors T.sub.1 and T.sub.3 is brought about by means of an interconnection line 6 and the connection of the gates of transistors T.sub.2 and T.sub.4 by means of interconnection line 8, said lines 6 and 8 being formed (FIG. 2) in an etched conductive layer 9, generally of polycrystalline silicon, which also is used for producing the various gates.
Moreover, as shown in FIG. 1, the drain D.sub.1 of transistor T.sub.1 is electrically connected to drain D.sub.3 of transistor T.sub.3, as well as to the gates G.sub.2 and G.sub.4 of transistors T.sub.2 and T.sub.4.
These connections, as shown in FIG. 2, are obtained by means of three electric contact holes 10, 12, 14, formed in an insulating material layer particularly silicon oxide (not shown). An interconnection line 16 formed in the more particularly aluminum conductive layer 18 ensures the connection between the drain D.sub.1 of transistor T.sub.1 and the drain D.sub.3 of transistor T.sub.3, said line 16 being respectively in contact with drain D.sub.1 and drain D.sub.3 by means of electric contact holes 10 and 14, as well as an interconnection line 19 formed in the etched conductive layer 9 which ensures the connection of active zones D.sub.1 and D.sub.3 to the gates of transistors T.sub.2 and T.sub.4, said line 19 being in contact with line 16 as a result of contact hole 12 made in said line 16.
In the same way as shown in FIG. 1, the drain D.sub.2 of transistor T.sub.2 is electrically connected by drain D.sub.4 of transistor T.sub.4 as well as to gates G.sub.1 and G.sub.3 of transistors T.sub.1 and T.sub.3.
As shown in FIG. 2, these connections are produced by means of three electric contact holes 20, 22, 24, formed in the insulating material layer. An interconnection line 26 formed in conductive layer 18 ensures the connection between drain D.sub.2 of transistor T.sub.2 and drain D.sub.4 of transistor T.sub.4, said line 26 being respectively in contact with drain D.sub.2 and drain D.sub.4 as a result of electric contact holes 20, 24, as well as an interconnection line 28 formed in the conductive layer 9 and ensuring the connection between active zones D.sub.2, D.sub.4 and the gates of transistors T.sub.1, T.sub.3, said line 28 being in contact with line 26 as a result of the contact hole 22 formed in said line 26.
Furthermore, sources S.sub.3, S.sub.4 of transistors T.sub.3, T.sub.4 are raised to earth potential (FIG. 1). These connections are assured by means of interconnection lines 30, 32, formed in the conductive coating 18, which are respectively in contact with sources S.sub.3, S.sub.4 of transistors T.sub.3, T.sub.4 via electric contact holes 34, 36 (FIG. 2), formed in the insulating layer.
As shown in FIG. 1, the activation of bistable element 2 of the storage cell is brought about by transistor T.sub.5, connected by its drain D.sub.5 to drain D.sub.3 of transistor T.sub.3, to drain D.sub.1 of transistor T.sub.1 and to gates G.sub.2, G.sub.4 of transistors T.sub.2, T.sub.4, or by transistor T.sub.6, whose drain D.sub.6 is connected to drain D.sub.4 of transistor T.sub.4, to drain D.sub.2 of transistor T.sub.2 as well as to gates G.sub.1, G.sub.3 of transistors T.sub.1, T.sub.3.
The connection between drain D.sub.5 of transistor T.sub.5 and drain D.sub.3 of transistor T.sub.3 is, as shown in FIG. 2, assured by an interconnection line 38 diffused in the substrate, whilst the connection between drain D.sub.6 of connection T.sub.6 and D.sub.4 of transistor T.sub.4 is assured by an interconnection line 40 diffused in the substrate. The other connections of drains D.sub.5, D.sub.6 of transistors T.sub.5, T.sub.6 are, as hereinbefore, provided by electric contact holes respectively 10, 12, 14 and 20, 22, 24 and the interconnection lines respectively 16, 19, 8, and 26, 28, 6.
The electric signals used for the selection of the storage cell are transmitted to gates G.sub.5, G.sub.6 of transistors T.sub.5, T.sub.6, which are electrically interconnected by interconnection line 42, formed in conductive layer 9, whilst the information to be stored in the selected storage cell or to be removed from said cell are transmitted by sources S.sub.5 and S.sub.6 of transistors T.sub.5 and T.sub.6. This information is carried by lines 44, 46 formed in the conductive layer 18 and in contact respectively with sources S.sub.5, S.sub.6 of transistors T.sub.5, T.sub.6, via electric contact holes 48, 50 (FIG. 2) and in the insulating layer and a second, more particularly aluminum conductive layer (not shown).
The presence of these six electric contact holes 10, 12, 14, 20, 22 and 24, which are necessary for producing the internal connections of the CMOS storage cell, bearing in mind the organization of the different layers constituting this cell, and particularly the crossing of the interconnection lines formed in the conductive layers 9, 18, limits the integration density of the storage cell.